1. Field of the Invention
The present invention relates to a method for manufacturing a capacitor in a semiconductor device; and, more particularly, a method for fabricating a capacitor having a bottom electrode, of which an upper part is smaller than a lower part.
2. Description of the Prior Art
An ECD (Electro-Chemical Deposition) technique is used to deposit the Pt layer for a bottom electrode of a capacitor, of which the size is decreased according to the increase of the integration density of the semiconductor device. To form the Pt layer for the bottom electrode, a Pt seed layer is formed on a semiconductor substrate. A predetermined lower structure is also formed, and an oxide layer pattern having an opening exposing the Pt seed layer is formed. The Pt layer is deposited on the Pt seed layer exposed in the opening.
At this time, a profile of a bottom electrode is determined by a profile of the opening in the oxide pattern formed by dry etch. The opening has the profile of the lower part. The lower part of the opening is relatively smaller than the upper part, by the characteristic of dry etch. As as shown in FIG. 1, the lower part of the bottom electrode is smaller than the upper part, according to the profile of the opening. Thereby, the electrical characteristics of the capacitor are deteriorated, because the step coverage of the dielectric layer and the top electrode, deposited on the bottom electrode, is poor.
It is, therefore, an object of the present invention to provide a method for fabricating a capacitor by improving an electrical characteristic in a semiconductor device.
In accordance with an aspect of the present invention, there is provided a method for fabricating a capacitor of a semiconductor device. The method includes the steps of forming a seed layer over a semiconductor substrate and forming multiple oxide layers on the seed layer, wherein a wet etching rate of the multiple oxide layers decreases as the layers go up.
There is also a step of forming a first opening for exposing the seed layer by selectively dry etching the multiple oxide layer. A second opening is formed by wet etching the lateral surface of the first opening where the width of the first opening is expanded. The lower part of the second opening is larger than the upper part.
The method further includes a step of forming a bottom electrode on the seed layer when it is exposed at the bottom of the second opening. The bottom electrode has an identical shape as the second opening, and the bottom electrode is formed with an ECD (Electro-Chemical Deposition) technique.
The seed layer is formed by removing the multiple oxide layers by wet etching. The seed layer is removed by dry etching. A dielectric layer is formed on the bottom electrode and a top electrode is formed on the dielectric layer.